Writing a Hypervisor in 1K Lines
Original: Writing a Hypervisor in 1k Lines
Key topics
The art of hypervisor development is being dissected after someone managed to cram one into just 1,000 lines of code, sparking a lively discussion around the intricacies of virtualization, particularly on RISC-V architectures. Commenters are debating the feasibility of optimizing page table walks using RISC-V Vector (RVV) instructions, with some arguing it's not a straightforward solution due to dependent loads. Meanwhile, others are seeking resources on hypervisors, with some recommending a mix of manufacturer manuals, source code, and seminal papers from VMware, Xen, and KVM to get both the big picture and the nitty-gritty details. The conversation highlights the complexity of virtualization and the value of exploring both historical microkernel literature and modern implementations.
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Discussion Activity
Moderate engagementFirst comment
4d
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Day 4
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Based on 14 loaded comments
Key moments
- 01Story posted
Aug 29, 2025 at 6:12 PM EDT
4 months ago
Step 01 - 02First comment
Sep 2, 2025 at 2:22 PM EDT
4d after posting
Step 02 - 03Peak activity
9 comments in Day 4
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Step 03 - 04Latest activity
Sep 10, 2025 at 12:53 AM EDT
4 months ago
Step 04
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Like, uni books won't give you an x86 manual because that wouldn't be neutral, but that's precisely the foundation of virtualization, from both a host and guest perspective.
You can read books on x86, but why not use some official intel manual?
Big picture for virtualization? There's many, it's a complex emerging phenomenon which placed a lot of asterisks on computation, is it used for security? Or to patch tech debt? or to provide backwards compatibility? Yes. What is the limit between isolation and efficiency? No one knows yet and there's many answers, you can activate shared cpu caching or disable Spectre mitigations for efficiency, or you can just forego virtualization as a whole and depend on application level multitenancy, which is not a separate topic at all in terms of virtualization, as you can see with tech like containers, and t1/t2 hybrids, it's a spectrum of virtualization, there is no hard line separating the virtualized from the bare metal.
practice: https://www.cse.iitb.ac.in/~mythili/virtcc/papers/vmware.pdf
For Aarch64, Arm's official guide is pretty good https://developer.arm.com/documentation/102142/latest/