Trigger Crossbar

Posted4 months agoActive4 months ago

zdw

89 points

18 comments

serd.esTechstory

excitedpositive

Debate

10/100

Hardware HackingFpga DevelopmentElectronics Design

Key topics

Hardware Hacking

Fpga Development

Electronics Design

The author built a 'Trigger Crossbar' device, a complex FPGA-based project, and shared their detailed experience, impressing the HN community with their problem-solving and engineering skills.

Snapshot generated from the HN discussion

Discussion Activity

Light discussion

First comment

Peak period

3-6h

Avg / period

2.6

Comment distribution18 data points

Loading chart...

Based on 18 loaded comments

Key moments

01Story posted
Sep 14, 2025 at 6:08 PM EDT
4 months ago
Step 01
02First comment
Sep 14, 2025 at 7:37 PM EDT
1h after posting
Step 02
03Peak activity
4 comments in 3-6h
Hottest window of the conversation
Step 03
04Latest activity
Sep 16, 2025 at 2:18 PM EDT
4 months ago
Step 04

Generating AI Summary...

Analyzing up to 500 comments to identify key contributors and discussion patterns

Discussion (18 comments)

Showing 18 comments

frainfreeze

4 months ago

1 reply

The "root canal" side quest was definitely something. Kudos to author

isoprophlex

4 months ago

    > The only thing left to do was solder it up (not trivial, given that I’m trying to hit a 250 μm diameter target at the bottom of a 1.6mm deep hole).

Shiiiit, absolutely heroic skill level.

nine_k

4 months ago

1 reply

Pretty epic. A very impressive case of building one's own tools, or, rather, a one-off tool that seems to do a simple thing. The most impressive aspect is, of course, handling various issues that normally would require making a new PCB, but the author never retreated.

kragen

4 months ago

1 reply

I imagine he'll post the files, so they won't be a one-off.

stephen_g

4 months ago

2 replies

They’re already linked from the article - https://github.com/azonenberg/triggercrossbar/

kragen

4 months ago

Thanks! I had missed that!

azonenberg

4 months ago

Yep. Although given all of the bugs, I don't recommend anyone try to build one without forking and making substantial design changes :)

philipallstar

4 months ago

1 reply

> Unfortunately, having all of the transceivers in a single quad was a bit limiting due to the 7 series clocking architecture: they share the same QPLL, which has to be at 10.3125 Gbps for 10Gbase-R operation. While the CPLLs can be configured freely, they have a lower Fmax which meant that the BERT / CDR trigger channels cannot operate at arbitrary frequencies above 6 Gbps (most notably, 8 Gbps operation for PCIe gen3 mode is not available).

I'm glad someone understands this.

stephen_g

4 months ago

1 reply

This one is especially tricky since even if you know what a phased lock loop (PLL) is, the terms CPLL and QPLL are specific to the arrangement of transceivers in these specific Xilinx FPGAs (7 series being one family of FPGAs which came before the UltraScale and then UltraScale+ series). There are four transceivers in a ‘quad’ which can either run from their ‘Channel PLL’ (CPLL) or the shared ‘Quad PLL’ that can run much faster to do basically double the line rate.

azonenberg

4 months ago

Yeah it's always tricky to decide how much detail to include in these posts. If I had gone on a whole explanation of the full 7 series GTX clocking architecture the post would easily have been another few pages in length.

thomasjb

4 months ago

1 reply

This is a really beautiful bit of kit, really like the case and the thought given to signing, but the analog side is really impressive too. Would it be viable to use the same hardware as a base for an NTP server?

azonenberg

4 months ago

You could build an NTP server with much less horsepower (and of course without all of the high speed I/O etc).

The ones from Leo Bodnar are decent.

baq

4 months ago

Soldered an ESP32 together with a couple I2C sensors the other week. Didn’t work. Read post, jaw hit floor, maybe I’ll revisit the project soon. Amazing.

kragen

4 months ago

This is very impressive.

thrtythreeforty

4 months ago

The author is Andrew Zonenberg. For those unfamiliar, this qualifies as a "medium complexity" (!) project for him. His stuff is always a great read.

a1o

4 months ago

This is super impressive. Additionally, I had never heard about ngscopeclient before. Amazingly cool software!

amluto

4 months ago

> My original plan had been to use their standard 1U folded sheet metal design, but I discovered too late, after boards were ordered, that it wasn’t going to work due to the 5mm corner mounting holes being inside the keepout area for the rear bend.

I wonder if a less annoying solution would have been to omit the mounting holes and then drill and tap them after the fact, possibly at a slight angle if the metal is out of plane there.

Liftyee

4 months ago

Amazing levels of depth and detail here. I wonder what sort of choices I need to make to eventually acquire a lab like this.

View full discussion on Hacker News

ID: 45243740Type: storyLast synced: 11/20/2025, 1:32:57 PM

Want the full context?

Jump to the original sources

Read the primary article or dive into the live Hacker News thread when you're ready.

Open link View on HN