Linus Torvalds Lashes Out at Risc-V Big Endian Plans

Posted3 months agoActive3 months ago

colejohnson66

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phoronix.comTechstory

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Risc-VLinuxComputer Architecture

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Linux

Computer Architecture

Linus Torvalds criticizes RISC-V's plans for big-endian support, sparking a debate about the relevance and implementation of endianness in modern computing.

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Oct 1, 2025 at 9:27 AM EDT
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Discussion (9 comments)

Showing 9 comments

beanjuiceII

3 months ago

2 replies

"lashes out" or actually just talks common sense

bell-cot

3 months ago

Yeah - but the phrase is both clicky, and a good warning for folks unfamiliar with Linus' communication style.

Diplomacy and tender feelings aside - the CEO yelling "HELL, NO!" can prevent an enormous amount of wasted time and talk.

freedomben

3 months ago

Lashing out and common sense aren't mutually exclusive. I.e you can lash out as someone with a message containing common sense information. I agree the headline is a bit exaggerated, but it's not incorrect.

I also don't think endianess is common sense. Maybe among experienced kernel developers it is, but even Linus had to Google to see what the argument was. I don't think Linus is common, inexperienced, or dumb

general1465

3 months ago

1 reply

Instead of adding support for Big Endian, maybe adding something like REV instruction in ARM would make more sense - https://developer.arm.com/documentation/dui0473/m/arm-and-th...

Then you can still run fine in Little Endian and convert BE->LE for protocols via single instruction

brucehoult

3 months ago

That has existed for the last four years in the `Zbb` extension which is implemented in the most common RISC-V Linux SoC (JH7110, 2023) and anything more recent implementing RVA22 e.g. the SpacemiT chips. Also the P550 ones such as EIC7700X.

The THead cores from 2019 (C906, C910) that precede the Zbb spec by a couple of years implement their own custom instruction.

The only reasonably common Linux core that doesn't have byte reverse is the 2018 U54, used in the HiFive Unleashed (~500 made) and the Microchip Polarfire Soc and PIC64GX ranges.

ksec

3 months ago

>RISC-V is enough of a mess with the millions of silly configuration issues already. Don't make it even worse.

This isn't going to end well on HN.

richardfey

3 months ago

I don't take sides on the opinion of BE vs LE, but why would the kernel devs be in charge of deciding how a hardware platform design would look like?

Are they in the design commitee for RISC-V?

Imagine the lawn mower deciding to stop running because it detects a type of grass that the lawn mower creators didn't like.

brucehoult

3 months ago

There are no such plans. Someone asked if there are plans.

usamoi

3 months ago

Not implementing the Zbb extension but implementing big-endian. That sounds like doing it the hard way.

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ID: 45437464Type: storyLast synced: 11/20/2025, 4:11:17 PM

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