Ibm Says Quantum Computing Error Correction Algorithm Can Run on Amd Chips
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reuters.comTechstory
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Quantum ComputingError CorrectionHardware Compatibility
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Quantum Computing
Error Correction
Hardware Compatibility
IBM claims its quantum computing error correction algorithm can run on conventional AMD chips, sparking discussion on the potential implications for quantum computing hardware; commenters ponder the technical details and potential applications.
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- ( [2506.03094] Tour de gross: A modular quantum computer based on bivariate bicycle codes https://arxiv.org/abs/2506.03094 )
- [2506.01779] "Improved belief propagation is sufficient for real-time decoding of quantum memory" (2025) https://arxiv.org/abs/2506.01779 :
> Abstract: [...] Relay-BP is inherently parallel, enabling rapid low-footprint decoding with FPGA or ASIC real-time implementations, similar to standard BP. A core aspect of our decoder is its enhancement of the standard BP algorithm by incorporating disordered memory strengths. This dampens oscillations and breaks symmetries that trap traditional BP algorithms.
- "QUEKUF: An FPGA Union Find Decoder for Quantum Error Correction on the Toric Code". ACM Transactions on Reconfigurable Technology and Systems (2025) https://dl.acm.org/doi/10.1145/3733239
necst/QUEKUF: "Union Find Decoder for Quantum Error Correction on the Toric Code": https://github.com/necst/QUEKUF