Adding Capability Hardware Enhanced Risc Instructions (cheri) to Linux
Posted3 months agoActive3 months ago
lwn.netTechstory
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LinuxCheriRiscSecurity
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Linux
Cheri
Risc
Security
The article discusses the addition of Capability Hardware Enhanced RISC Instructions (CHERI) to Linux, a technology aimed at improving memory safety, with the single comment reflecting a thoughtful and inquiring tone about its implications.
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- 01Story posted
Sep 25, 2025 at 2:00 AM EDT
3 months ago
Step 01 - 02First comment
Sep 25, 2025 at 2:41 AM EDT
41m after posting
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Sep 25, 2025 at 2:41 AM EDT
3 months ago
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ID: 45369710Type: storyLast synced: 11/17/2025, 1:12:47 PM
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Is the (page-level) NX bit almost capability based addressing?
Capability-based addressing: https://en.wikipedia.org/wiki/Capability-based_addressing